Dear BSIM Users, Thank you for your support of the BSIM models. We're releasing the BSIM4.0.0 model code today. This model is developed to explicitly address many issues in modeling sub-0.13 micron CMOS technology and RF high-speed CMOS circuit simulation. The plans and progress of the development were presented and discussed at serveral Compact Model Council (CMC) meetings in 1998 and 1999 period. Many inputs and serveral requests from those meetings were incorporated into the model. BSIM4 beta versoin was tested by CMC member companies and their feedback was incorporated into BSIM4.0.0. BSIM4.0.0 has the following major improvements and additions over BSIM3v3: (1) an accurate new model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications; (2) flexible substrate resistance network for RF modeling; (3) a new accurate channel thermal noise model and a noise partition model for the induced gate noise; (4) a non-quasi-static (NQS) model that is consistent with the Rg-based RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances. (5) an accurate gate direct tunneling model; (6) a comprehensive and versatile geometry-dependent parasitics model for various source/drain connections and multi-finger devices; (7) improved model for steep vertical retrograde doping profiles; (8) better model for pocket-implanted devices in Vth, bulk charge effect model, and Rout; (9) asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET at the user's discretion; (10) acceptance of either the electrical or physical gate oxide thickness as the model input at the user's choice in a physically accurate maner; (11) the quantum mechanical charge-layer-thickness model for both IV and CV; (12) a more accurate mobility model for predictive modeling; (13) a gate-induced drain leakage (GIDL) current model, available in BSIM for the first time; (14) an improved unified flicker (1/f) noise model, which is smooth over all bias regions and considers the bulk charge effect; (15) different diode IV and CV charatistics for source and drain junctions; (16) junction diode breakdown with or without current limiting; and (17) dielectric constant of the gate dielectric as a model parameter. We have been helped by the input from many users, especially the CMC member companies and their representatives. We would particularly like to thank the CMC members for proposing the geommetry-dependent parasitics model, which was drafted by Josef Watts and further enhanced by Jon Sanders. BSIM4.0.0 beta received intensive evaluation by the TI Mixed Signal Products group. Their testing materially and substantially improved the quality of the present prodution release. We would particularly like to thank Keith Green, Karthik Vasanth, William Liu, Britt Brooks, Doug Weiser, Brian Mounce, Jon Krick, Jim Hellums, Vinod Gupta, and Tom Vrotsos for their invaluable test effort. We would also like to thank Wenliang Zhang and Bob Daniels of Avant!, and John O'Donovan and Kristin Beggs of Cadence for bug reports. We appreciate these companies providing us with device data during the BSIM4 development: TI, Hitachi, AMD, IBM, and Conexant. BSIM4 research is partially supported by SRC, CMC, Conexant, Mentor Graphics and TI. The BSIM4 model was developed by Professor Chenming Hu, Research Engineer Weidong Liu, and graduate students Xiaodong Jin, Kanyu M. Cao and Jeff Ou. Sincerely, Chenming Hu ============================================================= Chenming Hu, TSMC Distinguished Professor of Microelectronics Dept. of Electrical Engineering and Computer Sciences University of California, Berkeley, CA, 94720 Email: hu@eecs.berkeley.edu ============================================================= The BSIM4.0.0 source code can be downloaded at http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html Technical Contact: Weidong Liu: liuwd@bsim.eecs.berkeley.edu