The scaling of CMOS devices faces increasing challenges in maintaining high drive currents and robustness.  As device dimensions decrease, series resistance in the source/drain and their contacts limits drive current and reduces the effectiveness of mobility enhancement technologies such as strained channels.  With dimensions down to the scale of several atoms, modern devices exhibit increasing amounts of variation in critical parameters such as threshold voltage.  Multi-gate device architectures and novel patterning techniques are being considered to improve robustness, especially for memories, which require extremely large design margins to achieve high chip yields.   

Transistor scaling has been the driving force for technology advancements in the semiconductor industry over the last few decades. In order to continue the historical progress, different classes of new processes and materials have been introduced to Si-based transistors in recent years — metal gate electrodes, high-permittivity (high-k) gate dielectrics, low-permittivity interlayer dielectrics, and SiGe source/drain.

Micro and Nano -Electro-Mechanical Systems (M/NEMS) Technology is being developed for MEMS integration on top of CMOS electronics, ultra-low-power digital logic integrated circuits, ultra-low-power memory applications and sensors. In the device group, the M/NEMS devices are fabricated at the UC Berkeley Microfabrication Facility using surface micromachining techniques.