The scaling of CMOS devices faces increasing challenges in maintaining high drive currents and robustness. As device dimensions decrease, series resistance in the source/drain and their contacts limits drive current and reduces the effectiveness of mobility enhancement technologies such as strained channels. With dimensions down to the scale of several atoms, modern devices exhibit increasing amounts of variation in critical parameters such as threshold voltage. Multi-gate device architectures and novel patterning techniques are being considered to improve robustness, especially for memories, which require extremely large design margins to achieve high chip yields. |