Recent Publications
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2011
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2011  
J. Jeon , W. Kwon , and T.-J. King Liu, “Embedded Memory Capability of Four-Terminal Relay Technology,” IEEE Trans. Electron Devices, in press.
C. Shin, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L. Chiu, C.-S. Fu, C.-T. Tsai, C. W. Liang, B. Nikolić, and T.-J. King Liu, “Quasi-Planar Bulk CMOS Technology for Improved SRAM Scalability,” Special Issue for ESSDERC 2010, Solid-State Electronics, 2011.

 

2010  
T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, and E. Alon, “Prospects for MEM Logic Switch Technology,” in IEEE Int'l Electron Devices Meeting (IEDM'10) Tech. Dig., in press.
J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. King Liu, “Perfectly Complementary Relay Design for Digital Logic Applications,” IEEE Electron Device Letters, vol. 31, no. 4, pp. 371-373, Apr. 2010.
J. Jeon, R. Nathanael, V. Pott, and T.-J. King Liu, “Four-Terminal Relay Design for Improved Body Effect,” IEEE Electron Device Letters, vol. 31, no. 5, pp. 515-517, May 2010.
R. Nathanael, V. Pott, H. Kam, J. Jeon, E. Alon, and T.-J. King Liu, “Four-Terminal Relay Body-Biasing Schemes for Complementary Digital Circuits,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 890-892, Aug. 2010.
J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. King Liu, “Seesaw Relay Logic and Memory Circuits,” IEEE/ASME J. Microelectromechanical Systems, vol. 19, no. 4, pp. 1012-1014, Aug. 2010.
V. Pott, H. Kam, R. Nathanael, J. Jeon, E. Alon, and T.-J. King Liu, “Mechanical Computing Redux: Relays for Integrated Circuit Applications,” Proc. IEEE, vol. 98, no. 12, pp. 2076-2094, Dec. 2010.
Hongki Kang, Dan Soltman, and Vivek Subramanian, "Hydrostatic Optimization of Inkjet-Printed Films," LANGMUIR, vol. 26, no. 13, pp. 11568–11573, 2010.
Alejandro de la Fuente Vornbrock, Donovan Sung, Hongki Kang, Rungrot Kitsomboonloha, and Vivek Subramanian, "Fully gravure and ink-jet printed high speed pBTTT organic thin film transistors," ORGANIC ELECTRONICS, vol. 11, no. 12, pp. 2037-2044, 2010.
C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazuré, B. Nikolić, and T.-J. King Liu, "Performance and Area Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22nm node,” IEEE Trans. Elec. Dev, vol. 57, no. 6, pp. 1301-1309, Jun. 2010.
C. Shin, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L. Chiu, C.-S. Fu, C.-T. Tsai, C. W. Liang, B. Nikolić, and T.-J. King Liu, “Tri-Gate Bulk CMOS Technology for Improved SRAM Scalability,” Proc. European Solid-State Device Research Conference (ESSDERC), pp. 142-145, Sep. 2010.
B. Nikolić, C. Shin, M. H. Cho, X. Sun, T.-J. King Liu, and B.-Y. Nguyen, “SRAM Design in Fully-Depleted SOI Technology,” IEEE International Symposium on Circuits and systems (ISCAS), pp. 1707-1710, Jun. 2010. (Invited paper)
C.H. Tsai, T.-J. King Liu, S.H. Tsai, C.F. Chang, Y.M. Tseng, R.Liao, R.M. Huang, P.W. Liu, C.T. Tsai, C. Shin, B.Nikolić, C.W. Liang, “Segmented Tri-Gate CMOS Technology for Device Variability Improvement,” IEEE International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), pp. 114-115, Apr. 2010.
Y. Tsukamoto, S. O. Toh, C. Shin, A. Mairena, T.-J. King Liu, B. Nikolić, “Analysis of the Relationship between Random Telegraph Signal and Negative Bias Temperature Instability,” IEEE International Reliability Physics Symposium (IRPS), pp. 1117-1121, May 2010.
R. A. Vega, T.-J. King Liu, "Dopant-Segregated Schottky Junction Tuning With Fluorine Pre-Silicidation Ion Implant," IEEE Trans. Elec. Dev., vol. 57, no. 5, pp. 1084-1092, May 2010.
R. A. Vega, V. C. Lee, T.-J. King Liu, "The Effect of Random Dopant Fluctuation on Specific Contact Resistivity," IEEE Trans. Elec. Dev., vol. 57, no. 1, pp. 273-281, Jan. 2010.
R. A. Vega, T.-J. King Liu, “DSS MOSFET with Tunable Source/Drain Extension Regions by Fluorine Pre-Silicidation Ion Implant (F-PSII),” IEEE Elec. Dev. Lett., vol. 31, no. 8, pp. 785-787, Aug. 2010.

 

2009  
V. Pott, H. Kam, J. Jeon, and T.-J. King Liu, “Improvement in Mechanical Contact Reliability with ALD TiO 2 Coating,” in Proc. AVS 56 th Int'l Symp., Nov. 2009, pp. 208-209.
H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, and T.-J. King Liu, “Design and Reliability of a Micro-Relay Technology for Zero-Standby-Power Digital Logic Applications,” in IEEE Int'l Electron Devices Meeting (IEDM'09) Tech. Dig., Dec. 2009, pp. 809-812.
R. Nathanael, V. Pott, H. Kam, J. Jeon, and T.-J. King Liu, “Four-Terminal Relay Technology for Complementary Logic,” in IEEE Int'l Electron Devices Meeting (IEDM'09) Tech. Dig., Dec. 2009, pp. 223-226.
Chun Wing Yeung; Padilla, A.; Tsu-Jae King Liu; Chenming Hu; , "Programming characteristics of the steep turn-on/off feedback FET (FBFET)," 2009 Symposium on VLSI Technology, pp.176-177, 16-18 June 2009
R. A. Vega, T.-J. King Liu, "Low Stanby Power Bulk MOSFET Design using High-k Trench Isolation", IEEE Elec. Dev. Lett., vol. 30, no. 12, pp. 1380-1382, Dec. 2009.
C. Shin, and T.-J. King Liu, “The right choice for 22nm SRAM,” Advanced Substrate News, #14 Winter 2009, Dec 2009.
C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, B. Nikolić, and T.-J. King Liu, “SRAM Yield Enhancement with Thin-BOX FD-SOI,” IEEE International SOI Conference, Oct 2009, (Best Paper Award and Best Student Award)
T.-J. King Liu, C. Shin, M. H. Cho, X. Sun, B. Nikolić, and B.-Y. Nguyen, "SRAM cell design considerations for SOI technology,” IEEE International SOI Conference, Oct. 2009. (Invited Paper)
C. Shin, X. Sun, T.-J. King Liu, "Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET," IEEE Trans. Elec. Dev., vol. 56, no.7, pp. 1538-1542, July 2009.
R. A. Vega, T.-J. King Liu, "Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study," IEEE Trans. Elec. Dev., vol. 56, no. 7, pp. 1483-1492, July 2009.
C. Shin, Y. Tsukamoto, X. Sun, and Tsu-Jae King Liu, “Full 3D simulation of 6T-SRAM cells for the 22nm node,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2009.
R. A. Vega, K. Liu, T.-J. King Liu, "Dopant-Segregated Schottky Source/Drain Double-Gate MOSFET Design in the Direct Source-to-Drain Tunneling Regime," IEEE Trans. Elec. Dev., vol. 56, no. 9, pp. 2016-2026, Sept. 2009.

 

2008  
R. A. Vega, T.-J. King Liu, "A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs," IEEE Trans. Elec. Dev., vol. 55, no. 10, pp. 2665-2677, Oct. 2008.
A. Padilla, Chun Wing Yeung, Changhwan Shin, Min Hee Cho, Chenming Hu, and Tsu-Jae King Liu, “Feedback FET:  A Novel Transistor Exhibiting Steep Switching Behavior at Low Bias Voltages”, to be presented at the 2008 IEDM conference.
A. Padilla, Sunyeong Lee, David Carlton, and Tsu-Jae King Liu, “Enhanced Endurance of Dual-bit SONOS NVM Cells Using the GIDL Read Method”, presented at the Symposium in VLSI Technology (2008)
A. Carlson, X. Sun, C. Shin, and T.-J. King Liu, “SRAM Yield and Performance Enhancement with Tri-gate Bulk MOSFETs,” IEEE Silicon Nanoelectronics Workshop (SNW), Jun. 2008.
C. Shin, A. Carlson, X. Sun, K. Jeon, and T.-J. King Liu, “Tri-gate Bulk MOSFET Design for Improved Robustness to Random Dopant Fluctuation,” IEEE Silicon Nanoelectronics Workshop (SNW), Jun. 2008.
C-H. Lin, M. V. Dunga, D. Lu, A. M. Niknejad and C. Hu, "Statistical Compact Modeling of Variations in Nano MOSFETs," IEEE International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, April 2008.

 

2007  
A. Padilla and Tsu-Jae King Liu, “Dual-bit SONOS FinFET Non-Volatile Memory Cell and New Method of Charge Detection”, presented at VLSI-TSA (Taiwan,2007)
R. A. Vega, T.-J. King-Liu, "Low Pressure Chemical Vapor Deposition of In Situ-Doped n- and p-Type Si1-xGex Films at 425 C," Journal of the Electrochemical Society, vol. 154, no. 9, H789-H793, 2007.
P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R. Harris, P. Kirsch, R. Choi, M. Chang, J. Lee, H. Hwang, H.-H. Tseng, R. Jammy, and T.-J. King Liu, Impact of Flash Annealing on the Performance and Reliability of High-k/ Metal-Gate MOSFETs for sub-45 nm Technology, IEEE IEDM, pp. 353-356, 2007.
D. D. Lu, M. V. Dunga, C-H. Lin, A. M. Niknejad and C. Hu, " A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation", Tech. Digest of 2007 IEEE International Electron Devices Meeting (IEDM), December 2007, pp. 565-568.
M. V. Dunga, C-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, "BSIM-MG: A versatile multi-gate FET model for mixed-signal design," 2007 Symposium on VLSI Technology. (Best Student Paper Award)
Woo Young Choi, Byung-Gook Park, Jong Duk Lee, and Tsu-Jae King Liu, "Tunneling Field Effect Transistor (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec", IEEE Electron Device Letters, Vol. 28, No. 8, pp. 743-745, August 2007.
Woo Young Choi, Hei Kam, Donovan Lee, Joanna Lai, and Tsu-Jae King Liu, “Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration,” International Electron Devices Meeting (IEDM), pp. 603-606, Washington DC, USA, Dec. 10~12, 2007.
W. Low, T.-J. King Liu, and R. T. Howe, “Characterization of polycrystalline silicon-germanium film deposition for modularly integrated MEMS applications,” IEEE Journal of Microelectromechanical Systems, Vol. 16, No. 1, pp. 68-77, 2007.
J. Lai and T.-J. King Liu, “Defect passivation by selenium ion implantation for poly-Si thin film transistors,” IEEE Electron Device Letters, Vol. 28, No. 8, pp. 725-727, 2007.
W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, Vol. 28, No. 8, pp. 743-745, 2007.
X. Sun, Q. Lu, H. Takeuchi, S. Balasubramanian, and T.-J. King Liu, “Selective enhancement of SiO2 etch rate by Ar ion implantation for improved etch depth control,” Electrochemical and Solid-State Letters, Vol. 10, No. 9, pp. D89-D91, 2007.
D. Lee, T. Seidel, J. Dalton, and T.-J. King Liu, “ALD refill of nanometer-scale gaps with high-k dielectric for advanced CMOS technologies,” Electrochemical and Solid-State Letters, Vol. 10, No. 9, pp. H257-H259, 2007.
A. Padilla, T.-J. King Liu, J. W. Hyun, I. Yoo, and Y. Park, “Dual-bit gate-sidewall-storage FinFET non-volatile memory cell and new method of charge detection,” IEEE Electron Device Letters, Vol. 28, No. 6, pp. 502-505, 2007.
C.C. Lo, J. Bokor, T. Schenkel, J. He, A. M. Tyryshkin, S. A. Lyon, "Spin-dependent Scattering off Neutral Antimony Donors in 28-Si Field-Effect Transistors ", Applied Physics Letters, 91, 242106 (2007)

 

2006  
M. V. Dunga, C-H. Lin, X. Xi, D. Lu, A. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model", IEEE Transactions on Electronic Devices, vol. 53, pp. 1971-1978, Sep. 2006.
C-H. Lin, MV Dunga, AM Niknejad, C Hu, "A Compact Quantum-Mechanical Model for Double-Gate MOSFET", International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1272-1274, October 2006. (Best Student Paper Award)
J Hu, X Xi, A Niknejad, C Hu,"On gate leakage current partition for MOSFET compact model", Solid State Electronics, vol. 50, issues 11-12, pp. 1740-1743, November-December 2006.
W. Low, T.-J. King Liu, and R. T. Howe, “Characterization of polycrystalline silicon-germanium film deposition for modularly integrated MEMS applications,” IEEE Journal of Microelectromechanical Systems, Vol. 16, No. 1, pp. 68-77, 2007.
L. Xu, C. Grigoropoulos, and T.-J. King, "High-performance thin-silicon-film transistors fabricated by double laser crystallization," Journal of Applied Physics, Vol. 99, pp. 0345408-1 to 0345408-6, 2006.
Q. Lu and T.-J. King Liu, “Trap energy levels associated with indium and boron impurities in SiO2,” Solid-State and Electrochemical Letters, Vol. 9, No. 9, pp. G296-G298, 2006.
K. Shin, W. Xiong, C. Y. Cho, C. R. Cleavelin, T. Schulz, K. Schruefer, P. Patruno, L. Smith, and T.-J. King Liu, “Study of bending-induced strain effects on MuGFET performance,” IEEE Electron Device Letters, Vol. 27, No. 8, pp. 671-673, 2006.
W. Xiong, C. R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T.-J. King Liu, “Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility,” IEEE Electron Device Letters, Vol. 27, No. 7, pp. 612-614, 2006.
A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T.-J. King Liu, “MOSFET hot-carrier reliability improvement by forward body bias,” IEEE Electron Device Letters, Vol. 27, No. 7, pp. 605-608, 2006.
A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, T.-J. King Liu, and C. Hu, “MOSFET design for forward body biasing scheme,” IEEE Electron Device Letters, Vol. 27, No. 5, pp. 387-389, 2006.
Schenkel T, Liddle JA, Bokor J, Persaud A, Park SJ, Shangkuan J, Lo CC, Kwon S, Lyon SA, Tyryshkin AM, Rangelow IW, Sarov Y, Schneider DH, Ager J, de Sousa R “Strategies for integration of donor electron spin qubits in silicon.” Microelect. Eng., 83 (4-9): 1814-1817 Apr. 2006
Schenkel T, Liddle JA, Persaud A, Tyryshkin AM, Lyon SA, de Sousa R, Whaley KB, Bokor J, Shangkuan J, Chakarov I “Electrical activation and electron spin coherence of ultralow dose antimony implants in silicon,” Appl. Phys. Lett., 88 (11): Art. No. 112101 Mar 13 2006

 

2005  
C-H. Lin, X. Xi, J. He, L. Chang, R. Q. Williams, M. B. Ketchen, W. E. Haensch, M. Dunga, S. Balasubramanian, A. M. Niknejad, M. Chan, and C. Hu, "Compact Modeling of FinFETs Featuring Independent-Gate Operation Mode", 2005 IEEE International Symposium on VLSI Technology, Systems and Applications, Hsinchu, Taiwan, May 2005. (Best Paper Award)
Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu, "Charge-Based Core and the Model Architecture of BSIM5", Proceedings of the Sixth International Symposium on Quality of Electronic Design (ISQED'05), pp.96-101, March 2005.
H. Takeuchi, A. Wung, X. Sun, R. T. Howe, and T.-J. King, “Thermal budget limits of quarter-micron foundry CMOS for post-processing MEMS devices,” IEEE Transactions on Electron Devices, Vol. 52, No. 9, pp. 2081-2086, 2005.
H. Takeuchi, M. She, K. Watanabe, and T.-J. King, “Damage-less sputter deposition by plasma charge trap for metal gate technologies,” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3, pp. 350-354, 2005.
S. Xiong, T.-J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp. 1859-1867, 2005.
S. Xiong, T.-J. King, and J. Bokor, “Study of the extrinsic parasitics in nano-scale transistors,” Semiconductor Science and Technology, Vol. 20, pp. 652-657, 2005.
Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 1, pp. 158-162, 2005.
H. Y. Wong, H. Takeuchi, T.-J. King, M. Ameen, and A. Agarwal, “Elimination of poly-Si gate depletion for sub-65nm CMOS technologies by excimer laser annealing,” to appear in IEEE Electron Device Letters, Vol. 26, No. 4, pp. 234-236, 2005.
Persaud A, Liddle JA, Schenkel T, Bokor J, Ivanov T, Rangelow IW “Ion implantation with scanning probe alignment,” J. Vac. Sci. Technol. B, 23 (6): 2798-2800 Nov.-Dec. 2005
Kwon S, Yan XM, Contreras AM, Liddle JA, Somorjai GA, Bokor J “Fabrication of metallic nanodots in large-area arrays by mold-to-mold cross imprinting (MTMCI),” Nano Lett., 5 (12): 2557-2562 Dec. 2005
Yan XM, Kwon S, Contreras AM, Koebel MM, Bokor J, Somorjai GA “Fabrication of dense arrays of platinum nanowires on silica, alumina, zirconia and ceria surfaces as 2-D model catalysts,” Catal. Lett., 105 (3-4): 127-132 Dec. 2005
Lin, J; Xuan, P; Bokor, J “Characterization of chemical vapor deposition growth yields of carbon nanotube transistors,” Jap. J. Appl. Phys. Pt. 1, 44 (9A): 6859-6861 Sep. 2005
Xiong, SY; King, TJ; Bokor, J “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain,” IEEE Trans. Elect. Dev., 52 (8): 1859-1867 Aug. 2005
San Paulo A, Bokor J, Howe RT, He R, Yang P, Gao D, Carraro C, Maboudian R “Mechanical elasticity of single and double clamped silicon nanobeams fabricated by the vapor-liquid-solid method,” Appl. Phys. Lett., 87 (5): Art. No. 053111 Aug. 1 2005
Qureshi N, Wang SQ, Lowther MA, Hawkins AR, Kwon S, Liddle A, Bokor J, Schmidt H “Cavity-enhanced magnetooptical observation of magnetization reversal in individual single-domain nanomagnets,” Nano Lett., 5 (7): 1413-1417 Jul. 2005
Persaud A, Park SJ, Liddle JA, Schenkel T, Bokor J, Rangelow IW “Integration of scanning probes and ion beams,” Nano Letters 5 (6): 1087-1091 June 2005.
Liu X, San Paulo A, Park M, Bokor J. “Characterization of acoustic vibration modes at GHz frequencies in bulk acoustic wave resonators by combination of scanning laser interferometry and scanning acoustic force microscopy,” 18th IEEE Int. Conf. on MEMS, Technical Digest, IEEE. 2005, pp. 175-8.
Yan XM, Kwon S, Contreras AM, Bokor J, Somorjai GA “Fabrication of large number density platinum nanowire arrays by size reduction lithography and nanoimprint lithography ,” Nano Lett. 5 (4): 745-748 April 2005.
Shiying Xiong, Bokor J. “Structural optimization of SUTBDG devices for low-power applications,” IEEE Trans. Elect. Dev., vol.52, no.3, March 2005, pp. 360-6.
San Paulo A, Liu X, Bokor J. “Scanning acoustic force microscopy characterization of thermal expansion effects on the electromechanical properties of film bulk acoustic resonators,” Appl. Phys. Lett., vol.86, no.8, 21 Feb. 2005, pp. 84102-1-3.

 

2004  
X. Xi, J. He, M. Dunga, H. Wan, M. Chan, C-H. Lin, B. Heydari, A. M. Niknejad, and C. Hu, (invited) "BSIM5 MOSFET model," 7th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, Oct. 2004.
X. Xi, J. He, M. Dunga, C-H. Lin, B. Heydari, H. Wan, M. Chan, A. Niknejad, C.Hu, "The next generation BSIM for sub-100nm mixed-signal circuit simulation", Custom Integrated Circuits Conference, p. 13-16,  Oct. 2004.
M. Chan, P. Su, H. Wan, C-H. Lin, S. K.-H. Fung, A. M. Niknejad, C. Hu, and P. K. Ko, "Modeling the Floating-Body Effects of Fully Depleted, Partially Depleted and Body-Grounded SOI MOSFETs ", Solid-State Electronics, Vol. 48, No. 6, pp. 969-978, June 2004.
J. He, X. Xi, M. Chan, C-H. Lin, A. Niknejad, C. Hu, " A Non-Charge-Sheet Based Analytical Model of  Undoped Symmetric Double-Gate MOSFETs Using SPP Approach", Proceedings of the 2004 IEEE International Symposium on Quality of electronic design, pp.45-50, April 2004.
D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, “Molybdenum gate technology for ultra-thin-body MOSFETs and FinFETs,” IEEE Transactions on Electron Devices, Vol. 51, No. 12, pp. 1989-1996, 2004.
S. Sedky, J. Schroeder, T. Sands, T.-J. King, and R. T. Howe, “Effect of excimer laser annealing on the structural properties of silicon germanium films,” Journal of Materials Research, Vol. 19, No. 12, pp. 3503-3511, 2004.
S. Sedky, R. T. Howe, and T.-J. King, “Pulsed-laser annealing, a low-thermal-budget technique for eliminating stress gradient in poly-SiGe MEMS structures,” Journal of Microelectromechanical Systems, Vol. 13, No. 4, 2004.
H. Takeuchi and T.-J. King, “Spectroscopic ellipsometry study on the oxidation of pure hafnium on silicon,” Journal of Vacuum Science and Technology A, July/August 2004.
M.-A. E. Eyoum and T.-J. King, “Low resistance silicon-germanium technology for modular integration of MEMS with electronics,” Journal of the Electrochemical Society, Vol. 151, No. 3, pp. J21-J25, 2004.
H. Takeuchi, P. Ranade, and T.-J. King, “Low temperature dopant activation technology using elevated Ge-S/D structure,” Applied Surface Science, Vol. 224, Issues 1-4, pp. 73-76, 2004.
H. Takeuchi and T.-J. King, “SCA (Surface Charge Analysis) of ultrathin HfO2, SiO2, and Si3N4,” Journal of the Electrochemical Society, Vol. 151, No. 2, pp. H44-H48, 2004.
W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith, D. Lewis, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, T.-J. King, and J. P. Colinge, “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron Device Letters, Vol. 25, No. 8, pp. 541-543, 2004.
H. Takeuchi, E. Quevy, S. A. Bhave, T.-J. King, and R. T. Howe, “Ge-blade damascene process for post-CMOS integration of nano-mechanical resonators,” IEEE Electron Device Letters, Vol. 25, No. 8, pp. 529-531, 2004.
C. Kuo, T.-J. King, and C. Hu, Bias polarity dependent effects of P+ floating gate EEPROMs,” IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 282-285, 2004.
Persaud A, Allen FI, Giccluel F, Park SJ, Liddle JA, Schenkel T, Ivanov T, Ivanova K, Rangelow IW, Bokor J “Single ion implantation with scanning probe alignment,” J. Vac. Sci. & Technol. B 22 (6): 2992-2994 Nov.-Dec. 2004.
Park SJ, Liddle JA, Persaud A, Allen FI, Schenkel T, Bokor J “Formation of 15 nm scale Coulomb blockade structures in silicon by electron beam lithography with a bilayer resist process,” J. Vac. Sci. & Technol. B 22 (6): 3115-3118 Nov.-Dec. 2004.
Shiying Xiong, Bokor J, Qi Xiang, Fisher P, Dudley I, Paula Rao, Haihong Wang, En B. "Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?," IEEE Trans. on Semic. Manuf., vol.17, no.3, Aug. 2004, pp. 357-61.
San Paulo A, Liu X, Bokor J. “Atomic Force Microscopy characterization of electromechanical properties of RF acoustic bulk wave resonators,” 17th IEEE Int. Conf. on MEMS 2004 Technical Digest. IEEE. 2004, pp. 169-72.
Park S-J, Persaud A, Liddle JA, Nilsson J, Bokor J, Schneider DH, Rangelow IW, Schenkel T. “Processing issues in top-down approaches to quantum computer development in silicon.” Microelect. Eng., vol.73-74, June 2004, pp. 695-700.
Schenkel T, Rangelow IW, Keller R, Park SJ, Nilsson J, Persaud A, Radmilovic VR, Grabiec P, Schneider DH, Liddle JA, Bokor J “Open questions in electronic sputtering of solids by slow highly charged ions with respect to applications in single ion implantation,” Nucl. Instrum. & Meth. In Phys. Res. B- 219: 200-205 June 2004.
Yagishita A, King TJ, Bokor J, “Schottky barrier height reduction and drive current improvement in metal source/drain MOSFET with strained-Si channel,” Jap. J. Appl.Phys. Part 1 43 (4B): 1713-1716 April 2004.
Xiong, S. and Bokor, J. "A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices," IEEE Trans. Electron Dev. 51 (2), 228-232, 2004.  
Wang, Y., Bokor, J., and Lee, A. "Maskless lithography using drop-on-demand inkjet printing method," Proc. SPIE 5374, p. 628-636, 2004.  
Tseng, Y.-C., Xuan, P., Javey, A., Malloy, R., Wang, Q., Bokor, J., and Dai, H. "Monolithic integration of carbon nanotube devices with silicon MOS technology," Nano Lett. 4 (1), 123-127, 2004.  
Shumway, M. D., Snow, E. L., Goldberg, K. A., Naulleau, P., Cao, H., Chandhok, M., Liddle, J. A., Anderson, E. H., and Bokor, J. "EUV resist imaging below 50 nm using coherent spatial filtering techniques," Proc. SPIE 5374, 454-459, 2004.  
Liu, H., Sin, J. K. O., Xuan, P., and Bokor, J. "Characterization of the ultrathin vertical channel CMOS technology," IEEE Trans. Electron Dev. 51 (1), 106-112, 2004.  

 

2003  
S. Lam, H. Wan, P. Su, P. Wyatt, C. Chen, A. Niknejad, C. Hu, P. Ko, and M. Chan, "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology," IEEE Electron Device Letters, vol. 24, pp. 251-253, April 2003.
C-H. Lin, P. Su, Y. Taur, X. Xi, J. He, A. M. Niknejad, M. Chan, and C. Hu, "Circuit Performance of Double-Gate SOI CMOS", International Semiconductor Device Research Symposium (ISDRS), pp. 148-149,
Washington D.C. , Dec. 2003.
C-H. Lin,  J. He, X. Xi, H. Kam, A. M. Niknejad, M. Chan, and C. Hu, "The Impact of Scaling on Volume Inversion in Symmetric Double-Gate MOSFETs," International Semiconductor Device Research Symposium (ISDRS), pp. 226-227, Washington D.C., Dec. 2003.
P. Su, S. Fung, P. Wyatt, W. Hui, A. Niknejad, M. Chan, and C. Hu, "On the body-source built-in potential lowering of SOI MOSFETs," IEEE Electron Device Letters, vol. 24, pp. 90-92, Feb. 2003.
Pin Su   Fung, S.K.H.   Wyatt, P.W.   Hui Wan   Mansun Chan   Niknejad, A.M.   Chenming Hu , "A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation", Proc. of the IEEE Custom Integrated Circuits Conference/, pp. 241-244, Sept. 2003.
M. Chan, X. Xi, J He, KM Cao, MV Dunga, AM Niknejad, PK Ko, C * *Hu, "Practical compact modeling approaches and options for sub-0.1 um CMOS technologies", Microelectronics Reliability, 43 pp. 399-404, 2003.
J. He, X. Xi, M. Chan, K. Cao, A. Niknejad, C. Hu, "A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET's Operation from Accumulation to Depletion Region," /Sixth International Conference on Modeling and Simulation of Microsystems/, San Francisco, CA, Vol.2, pp.302-305, February, 2003.
P. Su, S. K. H. Fung, P. W. Wyatt, H. Wan, A. M. Niknejad, M. Chan, C. Hu, "On the body-source built-in potential lowering of SOI MOSFETs" /IEEE Electron Device Letters, Vol. 24, No. 2, pp. 90-92, February 2003.
C. Kuo, T.-J. King, and C. Hu, “A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications,” IEEE Transactions on Electron Devices, Vol. 50, No. 12, pp. 2408-2416, 2003.
Invited: L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, “Extremely scaled silicon nano-CMOS devices,” Proceedings of the IEEE, Vol. 91, No. 11, pp. 1860-1873, 2003.
M. She and T.-J. King, “Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance,” IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 1934-1940, 2003.
D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King, and C. Hu, “Molybdenum gate work function engineering for ultra-thin-body silicon-on-insulator (UTB SOI) MOSFETs,” Japanese Journal of Applied Physics Part 1, Vol. 42, No. 4B, pp. 1979-1982, 2003.
X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King, and C. Hu, “Loop-Based Interconnect Modeling and Optimization Approach for Multigigahertz Clock Network Design,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, pp. 457-463, 2003.
C. Kuo, T.-J. King, and C. Hu, “Direct tunneling RAM (DT-RAM) for high-density memory applications,” IEEE Electron Device Letters, Vol. 24, No. 7, pp. 475-477, 2003.
H. Takeuchi and T.-J. King, “Scaling limits of hafnium-silicate films for CMOS gate-dielectric application,” Applied Physics Letters, Vol. 83, No. 4, pp. 788-790, July 2003.
M. She, H. Takeuchi, and T.-J. King, “Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory,” IEEE Electron Device Letters, Vol. 24, No. 5, pp. 309-311, 2003.
J.-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, and J. Bokor, “Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs, IEEE Electron Device Letters, Vol. 24, No. 3, pp. 186-188, 2003.
J.-S. Lee, D. Ha, Y.-K. Choi, T.-J. King, and J. Bokor, “Low-frequency noise characteristics of ultrathin body p-MOSFETs with Molybdenum gate, IEEE Electron Device Letters, Vol. 24, No. 1, pp. 31-33, 2003.
Xuan, P., She, M., Harteneck, B., Liddle, A., Bokor, J., and King, T.-J. "FinFET SONOS flash memory for embedded applications," IEDM Technical Digest, p. 609-612, 2003.
Xuan, P. and Bokor, J. "Investigation of NiSi and TiSi as CMOS gate materials," IEEE Electron Device Lett. 24 (10), 634-636, 2003.  
Xiong, S. and Bokor, J. "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Dev. 50 (11), 2255-2261, 2003.
Shumway, M. D., Naulleau, P., Goldberg, K. A., Snow, E. L., and Bokor, J. "Resist evaluation at 50 nm in the EUV using interferometric spatial frequency doubled imaging," Proc. SPIE 5037, p. 910-916, 2003.
Schenkel, T., Persaud, A., Park, S. J., Nilsson, J., Bokor, J., Liddle, J. A., Keller, R., Schneider, D. H., Cheng, D. W., and Humphries, D. E. "Solid state quantum computer development in silicon with single ion implantation," J. Appl. Phys. 94 (11), 7017-7024, 2003.  
Pu, N.-W. and Bokor, J. "Study of surface and bulk acoustic phonon excitations in superlattices using picosecond ultrasonics," Phys. Rev. Lett. 91 (7), 076101/1-4, 2003.  
Naulleau, P. P., Goldberg, K. A., Batson, P., Bokor, J., Denham, P., and Rekawa, S. "Fourier-synthesis custom-coherence illuminator for extreme ultraviolet microfield lithography," Appl. Opt. 42 (5), 820-826, 2003.
Naulleau, P., Goldberg, K. A., Anderson, E. H., Bokor, J., Harteneck, B., Jackson, K., Olynick, D., Salmassi, F., Baker, S., Mirkarimi, P., Spiller, E., Walton, C., O'Connell, D., Yan, P.-Y., and Zhang, G. "Static EUV micro-exposures using the ETS Set-2 optics," Proc. SPIE 5037, p. 36-46, 2003.
Naulleau, P., Goldberg, K. A., Anderson, E. H., Bokor, J., Harteneck, B., Jackson, K., Olynick, D., Salmassi, F., Baker, S., Mirkarimi, P., Spiller, E., Walton, C., O'Connell, D., Yan, P.-Y., and Zhang, G. "Printing-based performance analysis of the engineering test stand set-2 optic using a synchrotron exposure station with variable sigma," J. Vac. Sci. Technol. B 21(6), 2697-2700, 2003.  
Naulleau, P., Goldberg, K. A., Anderson, E. H., Bokor, J., Gullikson, E., Harteneck, B., Jackson, K., Olynick, D., Salmassi, F., Baker, S., Mirkarimi, P., Spiller, E., Walton, C., and Zhang, G. "Lithographic characterization of the printability of programmed extreme ultraviolet substrate defects," J. Vac. Sci. Technol. B 21(4), 1286-1290, 2003.  
Goldberg, K. A., Naulleau, P., Rekawa, S., Denham, P., Liddle, J. A., Anderson, E., Jackson, K., Bokor, J., and Attwood, D. "At-wavelength interferometry of high-NA diffraction-limited EUV optics," Proc. Eighth International Synchrotron Radiation Instrumentation Conf., August 28, 2003, pp. 4.
Goldberg, K. A., Naulleau, P., Rekawa, S., Denham, P., Liddle, J. A., Anderson, E., Jackson, K., Bokor, J., and Attwood, D. "At-wavelength interferometry of high-NA diffraction-limited EUV optics," Proc. Eighth International Synchrotron Radiation Instrumentation Conf., August 28, 2003, pp. 4.
Goldberg, K. A., Naulleau, P., Denham, P., Rekawa, S. B., Jackson, K., Anderson, E. H., Liddle, J. A., and Bokor, J. "EUV interferometry of the 0.3-NA MET optic," Proc. SPIE 5037, p. 69-74, 2003.  
Choi, Y.-K., Zhu, J., Grunes, J., Bokor, J., and Somorjai, G. A. "Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography," J. Phys. Chem. B 107 (15), 3340-3343, 2003.
Choi, Y.-K., Lee, J. S., Zhu, J., Somorjai, G. A., Lee, L. P., and Bokor, J. "Sublithographic nanofabrication technology for nanocatalysts and DNA chips," J. Vac. Sci. Technol. B 21(6), 2951-2955, 2003.  

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