BSIM-MG Frequently Asked Questions
Please send us your general questions regarding BSIM-MG; we will do our best to answer them on this page.
1. How to differentiate BSIM-CMG and BSIM-IMG?
- BSIM-IMG: 2 gates are biased at different bias.
- BSIM-CMG: all gates have the same bias, it can be double, triple, or all-around gate cases.
Fig. 1. A sample set of device architectures that CMG and IMG models can simulate.
2. What are the advantages of BSIM-CMG over BSIM4 model
• Scalability w.r.t. to FinFET related geometry … like TFIN , HFIN etc.
• Accurate predictions of variability effects in these parameters
• Smoothness of the model as against BSIM4 and accurate capacitances
• Accurate description of parasitic for FinFET geometry
• Multi-fin / Multi-finger demarcation in the model through NFIN , NF and incorporating these accurately in the model
• Quantum effects for thin-body is accurately captured in this model than in BSIM4
3. Does FinFETs have substrate bias? What is Ve? Is it backgate or substrate? What is bulk voltage if BULKMOD=1?
For BULKMOD=1, FinFET on Bulk: Ve is the voltage of the substrate node (bulk voltage). Ideally FinFET I-V /C-V characteristics should have almost no influence on ‘Ve’ for the fin is fully depleted. However under certain cases there could be a small amount of body-bias effect which we haven’t captured yet in the model and plan to do so in a future version. Otherwise, the substrate node is where the junction currents, GIDL/GISL, Impact Ionization current terminate.
For BULKMOD=0, FinFET on SOI: Ve is also the substrate node. Use of an additional back-gate to control Vth for FinFET hasn’t surfaced yet in use. Ve is merely used to terminate the parasitic capacitances from G/S/D to E through the buried oxide.
4. How is the handling BULKMOD=0 achieved? Is it like BSIMSOI?
a) Why is there no junction current?
b) Igb handling: For BULKMOD=0, why is Igb split as Igbs and Igbd? Shouldn’t it use SOI internal bulk node concept? The summation of all currents (Igb, junction, Iii, etc) is zero.
BULKMOD=0, i.e. FinFET on SOI Structure (as well as BSIM-IMG for FDSOI/UTBSOI devices) is handled very differently from BSIMSOI model. BSIMSOI models partially depleted SOI structure where the silicon was thick and there was always an un-depleted region below. This un-depleted region formed the internal bulk-node and any holes stored here (dynamically from junction currents and other leakage currents) were the root cause for history effects (floating body effects).
a) However in fully-depleted devices there is no place where the holes can stay and are flushed out of the source quickly. The body (or the back surface of the channel on the buried oxide) does float to a non-zero voltage, but this comes from the electrostatics of the device and is not because of holes stored like in PDSOI device. This is a major advantage for these devices. Our model assumes that the device is always fully-depleted (which is where a mature device with intrinsic channel doping would be targeted) and hence there is no need for the internal body node. Leakage currents like Impact Ionization, GIDL/GISL are assumed to flow between the source and drain as indicated by TCAD device simulations.
b) Along similar lines, the Igb component of the gate tunneling current will split into two components and flow into the source and drain …hence Igbs and Igbd.
5. What is typical device BULKMOD=0? Or BULKMOD=1?
Here is a list of matching device architecture and model switch w.r.t BULKMOD
-FinFET on Bulk: BULKMOD=1
-FinFET on SOI: BULKMOD=0
-Horizontal Nanowire FET: BULKMOD=0
-Vertical Nanowire FET: Depends on whether the bottom source drain diffusion tends to merge and close out the channel (then BULKMOD=0), else for very thick cylindrical gate structures (BULKMOD=1). Use TCAD to determine what is appropriate for your device
-No BULKMOD switch
6. Why is HFIN a model parameter, not an instance parameter? Is it treated similar to Tox?
HFIN is the height of the Fin for FinFET. HFIN is treated as model parameter for now for we believe that this parameter will be same value for a given technology. However in the future, if there is a multi-HFIN technology (just like multi-Vth technology is sometimes achieved using multiple oxide thicknesses), then HFIN should be elevated to instance parameter status.
7. What is NFIN? Why is NFIN used for binning selection?
NFIN is the number of Fins in a FinFET structure that shares the same source and drain. NF is the conventional number of fingers. Drain current calculated per fin would be multiplied with NF*NFIN to obtain the total current.
Fig. 2. An illustration of the difference between NF and NFIN.
Binning of NFIN parameter: BISM4 supported binning along parameters L and W. FinFETs being geometrically different, BSIM-CMG supports binning along L and NFIN. Due to lack of accurate process control at very small dimensions drain current might not scale with NFIN linearly. For example, if the on-current for a single fin FinFET is ION, then the on-current for a FinFET with 3 fins might not be 3*ION because TFIN or HFIN for the 3 fins that share the same source and drain might not be exactly the same. Hence, binning along NFIN has been introduced.
8. BSIM-CMG considers finite body doping; where and how is this information used?
Parameter COREMOD is used to switch between 2 different surface potential frameworks. COREMOD=1 uses a simple framework that assumes intrinsic channel doping. COREMOD=0 uses a framework that assumes finite body doping which is more accurate, for some amount of body doping could be used to set the Vth of a device in multi-Vth technologies. BSIM-CMG uses NBODY as an input (together with PHIG, gate work-function) and sets the Vth of the device. There is no VTH0 like parameter that was present in BSIM4.
Under fully-depleted channel assumption, the body-charge in the channel is fixed and is set by NBODY, TFIN, HFIN etc, for a FinFET. This body-charge does influence the potential distribution along the fin and influences various real device models like mobility, QM charge centroid model etc.
9. How is volume inversion included in BSIM-CMGl? What are the assumptions made in the surface potential based framework in the model?
Volume inversion arises because of the fully-depleted nature of the Fin (thin-body) where the entire Fin is under the control of the gate and takes on a non-zero potential. The inversion carriers are now present not only at the channel interface, but also throughout the Fin. The boundary conditions employed to solve the Poisson equation in this model automatically accounts for the volume inversion phenomenon.
The gradual channel approximation is also used here where we assume that the vertical field dominates over the horizontal field in order to reduce the Poisson equation to a 1-D equation; this leads in an analytical solution to the Poisson equation which should otherwise be solved numerically. However, the short channel effects that arise from the 2-D effects are accounted for separately.
10. BSIM4 used to model the drain current of sub-threshold region and inversion region separately. How does BSIM-CMG model the drain current?
The surface potential equation is solved twice analytically at the source and drain end of the channel. Using the Pao-Sah integral for drain current (refer “Operation and Modleing of MOS Transitor”, Y. Tsividis) and the surface potential equation we could obtain a closed form solution for the drain current. This drain current expression is a single piece and it is valid from sub-threshold to strong inversion.
Not mentioned in the manual is that fact that Vds is swapped appropriately to handle Vds<0 situation also. Vdsx maintains symmetry in some real device models as Vds passes through zero. Such a smoothing is not required for Vgs/Vgd for the swapping takes care of it. We might require a Vbsx in the future for implementing body effect.
BSIM-CMG and BSIM-IMG take care of symmetry issues that were present in BSIM4. There are no such issues with this model and is hence Analog/RF ready. The model passes Gummel Symmetry and AC Symmetry Tests.
Fig. 3. Gummel Symmetry (left) and AC Symmetry tests (right).
This model has been introduced to capture the asymmetry (ex: ION and Vth @Vds=Vdd could be different for forward and reverse modes) that might occur in some multi-gate device architectures. The asymmetry could occur due to asymmetric source/drain side underlap or asymmetric halo implants or highly asymmetric source/drain structure such as the vertical gate-all-around devices. While using different source side and drain side resistance helps, our studies indicated the physical need for more asymmetry in the model. BSIM-CMG105.03 incorporated some amount of this observed asymmetry in DIBL Vth Model and Vds dependence of Sub-threshold swing. We will roll-out more asymmetric parameters such as for Velocity Saturation model too soon.
For example, ETA0 parameter will have a reverse mode ETA0R parameter which could use a different value. The above Tanh() function ensures that the value switches from ETA0 to ETA0R in a smooth fashion without compromising the symmetry of the model.
13. Where can you read more about BSIMCMG?
We recommend the following resources to learn more about the BSIM Group’s new model, BSIMCMG:
- BSIM—SPICE Models Enable FinFET and UTB IC Designs here.
- M. V. Dunga, C-H. Lin, A. Niknejad, C. Hu, “BSIM-CMG: A compact Model for Multi-gate Transistors,” Chapter 3 in FinFETs and Other Multi-Gate Transistors, J. P. Colinge, Ed., Springer Science+Business Media, LLC. New York, NY , pp.113-153, 2007.
- BSIMCMG106.1.0 technical manual accessible here.
- Nanoscale CMOS Modeling, Mohan Vamsi Dunga